The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 1996
Filed:
Nov. 15, 1993
Applicant:
Inventor:
Shiva P Gowni, Mississippi State, MS (US);
Assignee:
Cypress Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395555 ; 395500 ; 3642328 ; 3642715 ; 327262 ;
Abstract
A programmable logic device (PLD) architecture that minimizes the skew in the outputs of PLD devices in response to input signal transitions. The architecture emulates the worst case response condition of the memory array portion of the PLD and builds it into a dedicated emulation signal path, which is in parallel with the signal path of the real data between the input and output of the PLD. The output of the emulation signal path then controls the real data output path and thus the output of the PLD. The PLD output equals the real data path output only when the output of the emulation signal path is valid.