The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 1996
Filed:
Jun. 12, 1995
Gary W Hoshizaki, Mesa, AZ (US);
Jerome A Grula, Chandler, AZ (US);
Nicholas J Spence, Mesa, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A method for building a compilable static RAM (SRAM). A central block structure (54) is formed which includes clock buffers (28), a delayed clock buffer (29), row address buffers (27), row deselect circuits (21), row driver circuits (22), output level translators, and a databus interface. A memory block macro (35) is built which includes a block of memory, precharge circuits, multiplexers, read/write multiplexers, and sense amplifiers. If multiple memory blocks are used a block deselect circuit (39) and row/block decoders (38) must be added to the memory block macro (35). A row and block deselection process is used in the SRAM architecture to simplify compilability and enhance speed.