The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 1996
Filed:
Dec. 03, 1993
Shinjiro Toyoda, Kanagawa, JP;
Hitoshi Ikeda, Kanagawa, JP;
Eiri Hashimoto, Kanagawa, JP;
Nobuaki Miyakawa, Kanagawa, JP;
Fuji Xerox Co., Ltd., Tokyo, JP;
Abstract
A device for calculating differences includes a difference circuit for generating difference signals .DELTA.x.sub.j =x.sub.j -x.sub.i, .DELTA.y.sub.j =y.sub.j -y.sub.i, and .DELTA.z.sub.j =z.sub.j -z.sub.i between coordinates of i having (x.sub.i, y.sub.i, z.sub.i) coordinate signals and coordinates of j having (x.sub.j, y.sub.j, z.sub.j) coordinate signals in an orthogonal coordinate system. The difference circuit includes an x-axis circuit, responsive to the x.sub.i and x.sub.j signals having a first circuit for receiving the x.sub.i coordinate signal and the x.sub.j coordinate signal and generating the .DELTA.x.sub.j ; a comparison circuit for comparing the x.sub.i and x.sub.j signals and determining whether the .DELTA.x.sub.j is less than a first set value -L.sub.x /2 corresponding to a length of a side of a virtual rectangular parallelepiped or greater than a second set value L.sub.x /2 corresponding to the length of the side of the virtual rectangular parallelepiped, L.sub.x being a value indicating the length of an elongated side in the x-axis direction of the virtual rectangular parallelepiped; an adder circuit for receiving the L.sub.x and .DELTA.x.sub.j and adding the L.sub.x to .DELTA.x.sub.j when .DELTA.x.sub.j is less than -L.sub.x /2; and a subtraction circuit for receiving the L.sub.x and .DELTA.x.sub.j and subtracting L.sub.x from .DELTA.x.sub.j when .DELTA.x.sub.j is greater than L.sub.x /2. The difference circuit includes y-axis and z-axis circuits similar to the x-axis circuit.