The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 1996

Filed:

Jan. 16, 1996
Applicant:
Inventor:

Haruhiko Fujii, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 93 ; 327166 ; 327291 ;
Abstract

A clock regeneration circuit capable of obtaining clocks each having an arbitrary duty. The clock regeneration circuit comprises a first D-type flip-flop having a clock terminal for receiving an input clock signal from an input terminal, and a data input terminal for receiving data of an H level, a second D-type flip-flop having a clock terminal for receiving the input clock signal from the input terminal, and a data input terminal for receiving data of an H level, a first delay circuit which receives an output from an output terminal of the first D-type flip-flop and outputs an output thereof to the reset terminal of the first D-type flip-flop, and a second delay circuit which receives the output from an output terminal of the first D-type flip-flop and outputs an output to a reset terminal of the second D-type flip-flop, wherein an output clock signal is outputted from an output terminal of the second D-type flip-flop to an output terminal.


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