Method of fabricating stacked capacitor of dram cell

Abstract

A stack capacitor capable of obtaining high capacitance in a limited area, thereby improving the integration degree of a semiconductor memory device and a process for fabricating the same. The process includes the steps of preparing a semiconductor substrate formed with a metal oxide semiconductor transistor, forming an insulating film over the transistor, forming a conductive material layer for a lower electrode plate on the insulating film such that the conductive material layer is electrically connected to the transistor, forming at least one conductive material layer for at least one additional electrode plate on the conductive material layer for the lower electrode plate such that it is spaced a predetermined distance apart from the conductive material layer for the lower electrode plate, forming at least one vertical column adapted to electrically connect the at least one additional electrode plate to the lower electrode plate, and sequentially coating a dielectric film and a plate electrode over the entire exposed surface of the resulting structure including the entire exposed surface of the additional electrode plate and the entire exposed surface of the at least one vertical column.