Method and apparatus for dynamic pole-zero reconfiguration for use with

Abstract

A second order PLL uses on-chip dynamically configurable compensation to permit varying loop bandwidth and damping ratio simultaneously in response to command signals. In a first embodiment, a type 2 PLL is compensated by synthesizing a two-pole lowpass filter, a zero, and a gain-programmable integrator. By appropriate selection of transfer function characteristics associated with each of these three building blocks, the open loop PLL transfer function may be remotely varied by scaling resistance or transconductance. In a second embodiment, a type 2 PLL is compensated using a simple series R-C in parallel with C configuration, wherein component selection results in a transfer function that permits relocation of a zero and a pole by varying a single resistance or transconductance. Such variation is preferably accomplished using ganged banks of resistors, remotely switched by associated metal-on-silicon transistors. In a hard disc data recovery application, wherein the recovered data bit rate varies as a function of read/write head position, generated control signals cause PLL compensation to be dynamically varied as a function of the data bit rate. This permits an optimized bandwidth and damping ratio to remain substantially constant over varying data bit rates. In other frequency agile applications, control signals commanding compensation configuration will be otherwise generated.