Method and apparatus for averaging clock skewing in clock distribution

Abstract

A system clock signal is delivered to a plurality of load devices by means of a common loop filter and delay line and a plurality of phase detectors and charge pumps each associated to a different load. The delay line provides a plurality of substantially identical phase corrected clock signals, each clock signal being coupled to the associated load device via an associated conductor member. In one embodiment, each conductor member comprises a loop consisting of a pair of conductors having substantially identical path lengths. The phase adjusted clock signals on the proximal end of the outbound conductor are coupled back as a first feedback signal to one input of the associated phase detector. Another feedback signal comprises the clock signal returned from the device node along the second conductor of the pair. A third input to the phase detector is the system input clock signal, which is also coupled to a reference input of the delay line. Each phase detector/charge pump combination generates a phase error correction signal corresponding to any delay associated with a given loop and device. The plurality of phase error correction signals are averaged in a loop filter and delay line, so that each phase corrected clock signal output from the delay line contains the average correction for all of the delays. In an alternate embodiment, the return loop is eliminated so that a single feedback signal representative of the delay induced by each load device is coupled to one input of a conventional two input phase detector. In this embodiment, the load effect on the distributed clock signals is averaged out.