The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 1996
Filed:
Jun. 12, 1995
Armand R Tanguay, Jr, Fullerton, CA (US);
B Keith Jenkins, Long Beach, CA (US);
University of Southern California, Los Angeles, CA (US);
Abstract
Computation-intensive applications such as sensor signal processing, sensor fusion, image processing, feature identification, pattern recognition, and early vision place stringent requirements on the computational capacity, size, weight, and power dissipation of modular computational systems intended for both embedded and high performance computer environments. Such ultra high speed, ultra high density computational modules will typically be configured with multiple processor, memory, dedicated sensor, and digital signal processing chips in close-packed multichip modules. The present invention relates to a novel architecture and associated apparatus for the development of highly multiplexed photonic interconnections between pairs of such electronic chips incorporated in vertical stacks within three-dimensional multichip module configurations. Vertical signal transmission through the chip substrates is accomplished by using a planar-waveguide-based optical power bus to provide a parallel array of beams to read out a modulator array that is flip-chip bonded to each silicon substrate. Local and quasi-local connectivity in the vertical dimension is accomplished by using diffractive optical structures that provide for both point-to-point interconnections and weighted fan-out within a local neighborhood. Global connectivity is incorporated by means of computer-generated volume holographic optical elements that are fabricated as a multilayer diffractive optical element. Several different architectural implementations of such computational modules are provided to address applications that include high-bandwidth two-dimensional displays, multilayer neural networks, image processors, multiple processors with access to shared memory, and rending engines for computer animation and graphics. In addition, subsystems of the computational-module architecture and apparatus are described that provide for compact optical readout of modulator-based flat panel displays.