The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 1996
Filed:
Jun. 06, 1995
Jurgen Hass, Sindelfingen, DE;
Rolf Hilgendorf, Boblingen, DE;
Siegfried Neuber, Sindelfingen, DE;
Thomas Schlipf, Holzgerlingen, DE;
Hartmut Ulland, Altdorf, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and system for the design verification of logic units capable of providing verification of a logic unit design prior to chip production. At least one test unit is coupled to a logic unit via an interface. The test unit includes a set of operations which are applied to the logic unit. The selection of test operations to be applied to the logic unit and the determination of the start times thereof are executed randomly and independently of each other. Thus, with the present method and system two parameters of the test operation generating event: the sequence of the test operations, and the temporal relationship between the test operations, are independently and randomly modified.