The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 1996
Filed:
Jun. 30, 1995
Mark W McDermott, Austin, TX (US);
John E Turner, Austin, TX (US);
Cyrix Corporation, Richardson, TX (US);
Abstract
A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration. In an alternative embodiment, the XNOR/XOR logic element can be used in a full adder to provide the sum output.