Processimg unit with programmable mis-aligned byte addressing

Abstract

A processing unit is provided that generates an address signal which specifies data on a per-byte basis and that further generates a set of byte enable signals which specify enabled bytes relative to the addressed byte. Both the byte enable signals and the address signal are provided to a memory control unit. The processing unit can thereby generate a single memory access to a misaligned memory address, while still specifying a variable number of enabled bytes. A control input provided to the processing unit controls whether a bus control unit of the processing unit generates single cycle memory accesses to misaligned addresses or two-cycle memory accesses to misaligned addresses. For memory accesses to static RAM, the memory control unit may deassert the control signal such that the processing unit generates two-cycle accesses on misaligned addresses. On the other hand, for memory accesses to dynamic RAM, the memory control unit may assert the control signal such that the processing unit generates single cycle accesses on misaligned addresses, unless a page boundary is encountered. The processing unit advantageously allows single cycle accesses to misaligned addresses to thereby accommodate increased system performance, and further supports broad compatibility with existing memory systems.