Fast acquisition clock recovery system

Abstract

A transceiver integrated circuit including a transmitter section having a phase-locked loop with an oscillator to provide an output at a predetermined transmission frequency, and a receiver section having a phase-locked loop with an oscillator used to provide a recovered clock from an incoming data signal. In a second mode when no incoming data is being received, the receiver oscillator is controlled in accordance with the transmitter oscillator to operate the receiver oscillator at the expected frequency of future data. Therefore, when data is received, the receiver oscillator is at the same approximate frequency as the incoming data thereby enabling fast acquisition by merely adjusting the phase of the receiver oscillator to the incoming data. In particular, the receiver and transmitter oscillators are identical current controlled oscillators that are operated in the second mode at the same approximate frequency by feeding the receiver oscillator with a current that is substantially equal to the loop current controlling the transmitter oscillator. Further, to provide higher slaving accuracy, a frequency detector is used to compare the outputs of the receiver and transmitter oscillators in the second mode, and to control the receiver oscillator into frequency synchronism with the transmitter oscillator.