The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 1996

Filed:

Mar. 21, 1995
Applicant:
Inventors:

Eric G Soenen, Plano, TX (US);

Loulis J Izzi, Plano, TX (US);

Thomas F Adkins, Coppell, TX (US);

Roman Staszewski, Garland, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518507 ; 365154 ; 365201 ; 36518905 ;
Abstract

An improved electrically erasable read only memory (EEPROM) includes a EEPROM cell and a static random access memory (SRAM) cell. Complementary pairs of complementary metal oxide semiconductor (CMOS) transistors connect the gates of transistors forming the EEPROM cell to either the corresponding data nodes of the SRAM cell or to a fixed read or nonzero test voltage. When formed into an array, it is not necessary to replicate differential sense circuitry in every cell. EEPROM transistor pairs are combined into columns which share a common sense latch. The nonsero test voltage allows for measurement of the actual threshold voltages (V.sub.T) of each EEPROM device individually.


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