The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 1996
Filed:
Mar. 05, 1993
John D Myers, Endwell, NY (US);
Jose L Rivero, Boca Raton, FL (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system for determining the optimal circuit design simulator schedule for debugging a digital electronic circuit design. The system characterizes all available circuit design simulators in terms of several parameters reflecting simulator speed and the time required to discover, isolate and fix a design error (bug). A cutover point is established for any pair of available simulators on the basis of these parameters. One simulator is progressively more efficient than the other beyond this cutover point, which is the desired time for scheduling substitution of the more efficient simulator during the debugging process. The system also permits 'what-if' evaluation of alternative debugging strategies in advance by creating alternative schedules in response to various characteristic parameters.