Bicmos power-up circuit with hysteresis

Abstract

A BiCMOS power-up circuit for delaying the operation of an extended circuit until the voltage available to the high-potential power rail of the extended circuit is sufficiently high that all elements of the extended circuit will be powered at a high enough voltage to function correctly. The power-up circuit of the present invention has its most direct application to three-state output buffers connected to a common bus, and in this context this circuit can maintain the output buffers in their high-Z, inactive state until the voltage available from the circuit-energizing power-supply has risen high enough that all of the stages of the buffers will operate correctly, and in particular will not be current-sourcing and current-sinking simultaneously. By the use of a primary control path and a secondary control path, the circuit of the present invention is able to manifest a hysteresis wherein during power-up the circuit of the present invention cedes control of the extended circuit at a power-supply threshold voltage V.sub.ThU which is higher than the threshold voltage V.sub.ThD at which the circuit re-asserts control during power-down. This avoids unnecessary turn-offs of the extended circuit occasioned by load-, noise-, and temperature-induced fluctuations in the high-potential power rail voltage, while allowing V.sub.ThU to be set quite high. By using bipolar and MOS transistors, the circuit of the present invention is able to make use of the specific advantages of each type of device.