Pagemap memory representation in risc processor printers

Abstract

Disclosed is a process and apparatus for pagemap memory representation in RISC controlled printers. The technique disclosed optimizes pagemaps in memory to minimize losses in processor efficiency of processors having data caches, TLB's and virtual memory, due to unavailability of desired data in first the data cache, then the random access memory. The technique is particularly applicable to RISC processors having a plurality of table lookaside buffers, each containing the address of a frame or page of memory, each frame comprising a finite number of bytes of data. This is accomplished by dividing the pagemap into one dimensional array of swaths of scans, each swath containing a two dimensional array of words in column major order. Each of said swaths having a height measured in scans which is a function of frame size, data cache line size and set associativity of the data cache, but which is an integral multiple of the number of words in a data cache line. The optimization of set associativity of data cache line utilization is accomplished by determining that the swath height divided by the number of words in a data cache line are not evenly divided by two.