Transmission error correction code appending device which can regulate a

Abstract

In a transmission error correction code appending device which receives a variable bit rate signal transmitted at a variable bit rate and having a plurality of information bytes, a transmitting circuit transmits, unless a timer circuit produces a time-out signal, the information bytes to a correction code appending circuit and transmits, when the timer circuit produces the time-out signal, zero bytes to the correction code appending circuit subsequently to the information bytes so that the information bytes and the zero bytes constitute first through N-th data bytes of first through M-th data groups, where each of M and N represents a predetermined plural and natural number. The correction code appending circuit consecutively supplies an interleaver with first through M-th blocks, each having the first through the N-th data bytes and first through P-th error correction code bytes as first through Q-th block bytes, where P represents a prescribed natural number, Q being equal to (N+P). An informing signal producer produces an informing signal when the interleaver receives the first block byte of the first block. The timer circuit produces the time-out signal when the timer circuit times a preselected time interval from a time instant at which the timer circuit receives the informing signal.