Reduced circuitry implementation for coverting two equal values to

Abstract

An apparatus and method for converting equal multi-bit digital values to non-equal multi-bit digital values that differ by one. The apparatus being an electronic circuit incorporated on an integrated chip, the circuit including an input register, a comparator, logic gates, and an output register. The input register receives at least two multi-bit digital values and supplies these values to the comparator. The comparator compares the values and determines if they are equal. The output of the comparator assumes one of either a logic HI or a logic LO state if the digital values are equal and the other of either a logic HI or logic LO state if the digital values are non-equal. The output of the comparator and the least significant bit associated with each of the multi-bit digital values received by the input register are input into the logic gates. In the event the two multi-bit digital values are non-equal, the logic gates pass the values through the circuit and to the output register in an unchanged form. In the event the two multi-bit digital values are equal, the logic gates manipulate the least significant bit of at least one of the multi-bit digital values so as to result in two non-equal values at the output register. According to the method of the invention, only the least significant bit of either of two equal multi-bit digital values will be changed and the resulting non-equal multi-bit digital values will differ by one.