Automated logic circuit design system

Abstract

A logic synthesis unit generates configuration data of a virtual logic circuit composed of virtual elements, or logic gates each of which carries only a functional definition, in order to realize a logic circuit functional description fed through an input unit. A logic transformation unit, referring to a standard cell library, performs the allocation of real elements for implementation to respective virtual elements to transform the virtual logic circuit into a real logic circuit having the same function as the virtual logic circuit. Then the logic transformation unit, referring to a timing analysis unit, selects a particular real element with a smallest driving capacity from among the real elements in the library performing the same function as an object virtual element and satisfying both fan-out restrictions and delay constraints, and allocates the real element thus selected to the virtual element. Configuration data of the resulting real logic circuit are output in the forms of circuit diagrams, real element connection information lists, and the like through an output unit.