The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 1996
Filed:
Feb. 22, 1995
Masahiro Ueda, Itami, JP;
Toshiaki Hanibuchi, Itami, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
The logic of an intermediate signal (Y.sub.1) goes high when an input signal (CI) makes an 'L' to 'H' transition, and then a transistor (Q.sub.1) turns on and a transistor (Q.sub.2) turns off. The input signal (CI) at a potential corresponding to the logic 'H' at a CMOS level has been applied to the gate of an NMOS transisitor (N.sub.1), and the NMOS transistor (N.sub.1) turns on rapidly. At this time, only current flowing through the base of an output transistor (Q.sub.0) flows through parallel connection of a resistor (R.sub.2) and an on-resistance of the NMOS transistor (N.sub.1). Since the NMOS transistor (N.sub.1) is on, the base potential of the output transistor (Q.sub.0) is raised if the resistor (R.sub.2) has a high resistance, and current fed from the output transistor (Q.sub.0) increases, thereby raising the emitter potential of the output transistor (Q.sub.0). Then the logic of an output signal (EO) goes high. Power consumption of an output buffer circuit is reduced.