Digital timing recovery method and apparatus for a coded data channel

Abstract

A digital timing recovery circuit for rapid acquisition and synchronization of sampling clock phase in a data playback signal processing channel. The filtered playback signal in a (1,7)ML coded playback channel is sampled at the rate of one sample per bit window and the digitized sample values are processed with a (1,7)ML decoding procedure to produce decoded bits. A digital timing recovery circuit of this invention uses the digitized sample values directly to control the sampling clock phase by computing a digital phase error signal (PES) that is a constant function of phase error independent of data pattern. The PES depends only on the adjacent samples before and after a peak signal value. These 'side-samples' contain maximal timing information because they occur at the steepest slope of the read-back signal and are thus most sensitive to clock phase error. Both side-samples of every pulse are weighted uniformly, independent of data pattern, thereby maximizing available phase information and ensuring the rapid acquisition and convergence of the sampling clock phase.