The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 1996
Filed:
Dec. 30, 1994
Isaya Sobue, Kasugai, JP;
Fujitsu Limited, Kawasaki, JP;
Fujitsu VLSI Limited, Kasugai, JP;
Abstract
In a semiconductor memory device with redundant configuration, a redundant address detection circuit is additionally provided between an I/O buffer and a read/write circuit coupled to a memory cell array. The detection circuit receives both a signal indicating the detection of redundancy from a redundant address setter and a signal instructing a test mode for the memory device, and selectively inverts the logic of data associated with the redundant cell. When the data is supplied to memory cells through the redundant address detection circuit under test mode conditions, only data involved in a redundant address is inverted in logic and is written into a redundant cell. Subsequently, a tester reads out the write data of all memory cells to produce a bit map indicating the address of the inverted data and allowing the tester to detect the address of redundant memory cells.