Signal voltage level conversion circuit and output buffer circuit

Abstract

A signal voltage level conversion circuit has a configuration in which all transistors can be produced, during the semiconductor fabrication process, so that their gate-source, gate-drain, and gate-substrate voltages are within the 3v voltage tolerance range. The signal voltage level conversion circuit converts input signals with a narrow logical amplitude of 0.about.3v to output signals with a wide logical amplitude of 0.about.5v. The input signal Vin, 0.about.3v, is temporarily converted into a mediator signal Vm, approximately 3.about.5v by a mediator signal generation circuit. An output buffer circuit then converts mediator signal Vm to output signal Vout of 0.about.5v. In the mediator signal generation circuit and the output buffer circuit, application of voltage is relaxed on a plurality of transistors, so that all transistors are maintained within the 3v voltage tolerance range.