Clock signal generation arrangement including digital noise reduction

Abstract

A clock signal generation arrangement for generating clocking signals for use in a fault-tolerant computer system generates a timing signal in response to a common clock signal. The clock signal generation arrangement comprises a system clock signal generator and a clock signal recovery circuit interconnected by a plurality of clock signal transfer lines. The system clock signal generator generates, in response to a common clock signal, a plurality of system clock signals preferably of uniform frequency and phase for transmission over a like plurality of clock signal transfer lines. The clock signal recovery circuit receives the system clock signals from the clock signal transfer lines and generates a unitary timing signal. The clock signal recovery circuit includes a voting circuit, a latch circuit and a latch control circuit. The voting circuit generates a voted clock signal having signal transitions that are generally aligned with transitions of a majority of the system clock signals. The latch circuit has alternating set and reset conditions in response to transitions of the voted clock signal, and generates the timing signal to have transitions corresponding to the latch circuit's respective set and reset conditions. Finally, the latch control circuit inhibits the latch circuit from transitioning between its set and reset conditions for a selected time period after a previous transition therebetween, so that the latch circuit will be insensitive to noise in the voted clock signal following such a transition.