The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 1996

Filed:

Nov. 29, 1994
Applicant:
Inventors:

Thoru Ozaki, Tokyo, JP;

Kazumasa Sunouchi, Kanagawa-ken, JP;

Seiichi Takedai, Tokyo, JP;

Yoshiyuki Shioyama, Kanagawa-ken, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257304 ; 257305 ; 257303 ; 257506 ;
Abstract

A dynamic RAM array comprises a substrate, a plurality of semiconductor island regions and a trench region formed on the substrate, each island region being surrounded by the trench region, and the trench region having wider trench portions and narrower trench portions, an insulating layer formed on the trench region, capacitors refilled in the wider trench portions, each capacitor having a plate electrode, a capacitor insulating layer and a storage node electrode, refilled layers formed in the narrower trench portion, for forming field isolation regions, MOS transistors formed on the island region, each MOS transistor having a source, a drain and a gate as word line, one of the source and drain being coupled with the storage node electrode, and bit lines perpendicular to the word line, being coupled with the other of the source and drain.


Find Patent Forward Citations

Loading…