Mechanism and protocol for maintaining cache coherency within an

Abstract

An integrated processor includes CPU core, cache memory, and cache controller coupled to a local bus via a local bus interface. The integrated processor further includes memory controller for coupling system memory to the local bus, and a bus interface unit for coupling external peripheral devices to the local bus. The cache controller includes an address tag and state logic circuit which keeps track of a physical address in system memory which corresponds to each entry within cache memory. Address tag and state logic circuit contains state information that indicates whether each cache line is valid and/or dirty. The cache controller includes a snoop control circuit which monitors the local bus to determine whether a memory cycle has been executed by an alternate bus master. During such a memory cycle of an alternate bus master, a comparator circuit determines whether a cache hit has occurred. If a cache read hit occurs with respect to a dirty cache line, the cache controller asserts an inhibit signal which causes the memory controller to ignore the cycle. The read request is instead serviced by the cache controller by providing the requested data from the cache memory to local bus 112. If a cache write operation occurs, data is written into the system memory via system memory controller, and the data is concurrently latched into the corresponding line of the cache memory. The status of cache line may further be updated to clean if the data transfer encompassed a complete cache line.