The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 1996

Filed:

Feb. 08, 1995
Applicant:
Inventors:

David Staab, San Jose, CA (US);

Nader Vijeh, Cupertino, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B / ;
U.S. Cl.
CPC ...
375213 ; 375214 ; 370 131 ; 370 14 ;
Abstract

A discrete integrated repeater device and port MAU/AUI functions shares resources among its several ports. The device includes a single multi-bit free running counter providing preselected timing intervals to a plurality of latches. A signal undergoing measurement clears the latch while a preselected timing signal sets the latch. Receipt of a timing signal at a set latch indicates success or failure of some particular condition under test. The device satisfies an IEEE 802.3 specification for execution of a link integrity test. The device is also able to selectively disable or enable the link integrity test function for particular ports. A plurality of latches, one associated with each port, is set upon carrier sense detection at the particular port. A token passing mechanism implemented with a daisy chained line coupled to each latch enables a polling of each latch to provide carrier sense information about each port in a serial format. The device shares a single PLL among all its ports by producing a logical sum of carrier sense inputs to enable activation of the PLL. A collision indication signal will override operation of the PLL to ensure data integrity and to allow the PLL to reacquire lock on its reference clock.


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