The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 1996
Filed:
Sep. 25, 1995
Robert H Miller, Jr, Loveland, CO (US);
Craig A Heikes, Fort Collins, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A system and method for quiescent current testing of dynamic logic circuitry. Nodes shorted to ground are detected during a dynamic pre-charge state. Nodes shorted to a power supply potential are detected by driving all nodes of interest to ground during a dynamic evaluation phase. Nodes of interest are driven to ground directly by one additional transistor per node or indirectly by logical propagation from upstream nodes. As a result, only two current measurements are needed for all shorted node faults, even for pipelined systems with multiple clocks. There is no need for input test signal sequences and no need for signal propagation to outputs for detection. Specific embodiments are provided for single-rail logic, single-rail pipelined systems, dual-rail logic and dual-rail pipelined systems. For single-rail pipelined systems, optional transistors between stages enable preservation of logical states during testing. For dual-rail logic, storage nodes and static nodes are forced to a logical state that is not possible during normal operation. For pipelined dual-rail logic, testing of alternate stages inherently preserves the logical state of the system during testing.