The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 1996
Filed:
Apr. 04, 1994
Stuart Rapoport, Washington, DC (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A processor-based Array Built-in Self Test (ABIST) circuit that generates self-test patterns for high speed SRAMs or DRAMs having a short access time. The circuit includes three main blocks: a conventional address generator for generating self-test addressing signals, a subset of which are used by a control logic main block. This control logic block forces proper signal sequencing of the processing main block during the ABIST mode. The processing main block includes, preferably, three generators for preparing signals for use during the next cycle. These signals are respectively stored in two latches to generate the corresponding expected output data one cycle later. The processor-based ABIST circuit allows for faster data generation, minimal semiconductor area consumption, extended programmability and full compatibility.