Variable length coder and variable length decoder

Abstract

A variable length coder and a variable length decoder. The variable length coder comprises a plurality of shifters, each of which inputs a corresponding one of a plurality of codewords and a plurality of codelengths, rotates the corresponding codeword by a desired length for interconnection of the codewords and outputs masking bits designating a position of the corresponding codeword to be rotated, a first OR gate for ORing output codewords from the shifters, a second OR gate for ORing output masking bits from the shifters, a word/mask register for latching output codeword bits from the first OR gate when corresponding output masking bits from the second OR gate are enabled to '1', and an FIFO memory for storing an output of the word/mask register and outputting variable length-coded data. The variable length decoder comprises a data shifter for shifting input data in response to a previous codelength and a matching signal, a decoding circuit for discriminating a matched state of output data from the data shifter according to the previous codelength to generate a current codelength, the matching signal and a decoded word, and a shift controller for controlling a shifting amount of the data shifter in response to the current codelength and the matching signal from the decoding circuit and outputting the previous codelength.