Dual conversion decoder

Abstract

A decoder has first and second decoder circuits for producing dual sets of outputs. The first decoder circuit is responsive to input lines B.sub.1 -B.sub.n representative of a binary value x and has first outputs Z.sub.1 -Z.sub.m where m=2.sup.n. In response to the value x applied to the first decoder, output line Z.sub.x+1 is set high while the remainder are set low. The second decoder circuit comprises m transmission gates serially connected between a first and a second potential. The transmission gates are each directly driven by a respective one of said first outputs Z.sub.1 -Z.sub.m. The second decoder circuit generates second outputs Y.sub.1 -Y.sub.m-1 at junctions of the transmission gates. In response to the value x applied to the first decoder, x number of the outputs Y.sub.1 -Y.sub.m-1 are set high beginning with the least significant output Y.sub.1 and continuing consecutively up to the output Y.sub.x with the remainder being set low.