Reprogrammable programmable logic array

Abstract

A reprogrammable programmable logic array comprising a first write module for inputting data to be written and data to be compared, an AND CAM cell array block for, in a write mode, sequentially storing the write data from the first write module and, in a match mode, comparing the comparison data from the first write module with its pre-stored data and generating match signals in accordance with the compared result, a first address module for, in the write mode, generating sequential addresses and supplying the generated sequential addresses to the AND CAM cell array block, a second write module for inputting data to be written in the write mode, an OR CAM cell array block for storing sequentially the write data from the second write module in the write mode and detecting its pre-stored data corresponding to the match signals from the AND CAM cell array block in the match mode, a second address module for, in the write mode, generating sequential addresses and supplying the generated sequential addresses to the OR CAM cell array block, and an output module for transferring the output data from the OR CAM cell array block externally in the match mode. The reprogrammable programmable logic array further comprises a buffer module for buffering the match signals from the AND CAM cell array block.