Method of fabricating ic chips with equation estimated statistical

Abstract

Within an integrated circuit chip, digital logic gates are intercoupled by signal lines called nets. If one net (called the 'victim net') has several segments that respectively lie next to several other nets (called 'aggressor nets'), then a certain amount of crosstalk voltage will be coupled into the victim net by each of the aggressor nets; and that can cause a malfunction. But with the present invention, a process is provided whereby an integrated circuit chip is physically laid out and built such that the total crosstalk voltage which is coupled into the victim net by all of the aggressor nets is kept within an acceptable level. This process includes a repetitive cycle where during each cycle, a previously tried layout is modified, and the crosstalk which is coupled into the victim net in the modified layout is estimated by means of an equation. In one embodiment, the equation estimates the mean crosstalk voltage which is coupled by each aggressor net separately; and in each repetitive cycle, the estimation is made separately for each aggressor net. In another embodiment, a different equation estimated the total mean crosstalk voltage which all of the aggressor nets together couple into the victim net; and in each repetitive cycle, this estimation is made only a single time.