Circuit for latching data signals from dram memory

Abstract

A circuit for latching data signals emanating from a DRAM memory for an extended period of time. The circuit is implemented on an ASIC chip which is positioned external to an FPM DRAM-type memory device. The circuit is organized to have a system transceiver, a memory transceiver, a data-in bus, a data-out bus, and control logic. The data-in bus is directly connected to a memory processor or controller through the system transceiver and the data-out bus is directly connected to the memory through the memory transceiver. The data-in bus is connected to the memory through a tri-state buffer positioned in the memory transceiver and the tri-state buffer is normally in an on position thereby normally connecting the data-in bus to the memory. The data-out bus is connected to the memory processor through a tri-state buffer which is normally in an off position. Hence, the circuit is normally configured to write data. In a read cycle, the data-in bus is isolated from the memory and the data-out bus is connected to the memory processor by manipulation of the tri-state buffers. The data is then latched in the latch on the data-out bus for an extended time period, e.g., until the memory processor sends a CAS signal to the memory and the circuit initiating a subsequent read cycle.