Method and apparatus for determining the timing specification of a

Abstract

The invention accepts user input that describes the circuit elements of a digital circuit and the interconnections between those elements. Based upon the user input, the invention computes the maximum setup and hold times for each data input of the integrated circuit. First, maximum and minimum delays from the clock inputs to the storage elements on the integrated circuit. Similarly, the maximum and minimum delays from the data inputs of the integrated circuit to each level one storage element are determined where a level one storage element is defined as a storage element that has no other storage elements interposed between it and a data input. For each data input/level one storage element pair, the setup time is computed based upon the previously calculated maximum data delay and minimum clock delay and the required setup time for the element. The desired setup time for a data input is the maximum setup time over all the level one storage elements coupled to that data input. Hold times are similarly determined except that the hold time is based upon the previously calculated maximum clock delay and minimum data delay and the required hold time for the element.