Overvoltage protection

Abstract

The present invention provides input and output buffers which block the charge leakage from the bus to the internal power supply when the bus voltage exceeds the internal power supply voltage or when the buffer is powered down. An isolation transistor is connected in series with a pull-up transistor between the internal power supply and the output terminal which is connected to the bus. A circuit that controls the pull-up transistor in response to an enable signal and a data input signal, controls also the isolation transistor so that when the driver is enabled and the pull-up transistor is on, the isolation transistor is also on allowing the pull-up transistor to drive the output terminal. A transistor between the circuit and the isolation transistor gate isolates the gate from the circuit when the driver is disabled. Thus, when the driver is disabled, the circuit does not control the isolation transistor. Instead, the isolation transistor is controlled by a pass-through transistor connected between the gate of the isolation transistor and the output terminal. When the driver is enabled, the pass-through transistor is off. When the driver is disabled and the output terminal voltage exceeds the predetermined value, the pass-through transistor turns on to turn off the isolation transistor. The isolation transistor is a PMOS transistor in some embodiments. The isolation transistor drain and backgate are connected to turn off the drain/backgate diode.