The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 1996
Filed:
Apr. 17, 1995
Kuo-Tung Chang, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
Flash EEPROM cells having merged select/control gates may be formed, so that the portions of the channel regions that correspond to select transistors are formed after spacers are formed but prior to patterning a merged select/control gate layer. Because the portions of the channel regions that correspond to the select transistors are not determined by the patterning of the merged select/control gate layer, misalignment of the mask used to pattern the merged select/control gate layer does not affect the size of the select transistor portion of the channel region. The spacers may be left on over the substrate in the finished devices thereby saving at least one processing step. The memory structure may also be used in other EPROM-type memory cells, such as individually erasable EEPROMs and EPROMs that are not electrically erasable.