The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 1996

Filed:

Jan. 17, 1995
Applicant:
Inventor:

James L Gates, Lake Oswego, OR (US);

Assignee:

Flir Systems, Inc., Portland, OR (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01J / ;
U.S. Cl.
CPC ...
25037008 ; 2503381 ; 2503384 ; 250332 ;
Abstract

A micro-bolometric infrared (IR) staring array is described. The active element in each pixel within a two-dimensional array is a device having a selectively forward-biased p-n junction, e.g. a selectively biased diode. Each diode in the array serves as both an IR energy detecting element and a switching element. Each diode in a given row of the IR pixel array to be sensed, or read, is driven at a constant voltage, rendering its IR response highly controllable in the forward biased operating curve of the diodes in the addressed row. Diodes not being driven are, due to their reverse bias, in their off state producing minute leakage current and thus make no significant contribution to the sensed current representing a given pixel's IR exposure. The row-addressed driven or active diodes are sensed column by column by sample and hold techniques to produce a two-dimensional IR pixel image of a target. This simplifies the geometries as well as the cell structures while increasing the fill ratio to greater than approximately fifty percent. Moreover, manufacturing yields are greatly improved because of the topologic and process simplicities and compatibility with standard integrated circuit processes.


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