Reflexively sizing memory bus interface

Abstract

A reflexively scaling memory bus interface system and method allows the implementation of an ISA bus peripheral card that will effectively operate within the decoded memory space of another sixteen bit card while using only the external memory components required for an eight bit interface. The same peripheral card will also be compatible in a system with other eight bit cards located in a corresponding memory space. The reflexively sizing memory bus interface responds automatically to memory accesses that vary in data bus width (i.e., eight or sixteen bits) by directly or indirectly monitoring feedback signals from other devices on the bus. This technique solves the problem of integrating eight and sixteen bit cards on the ISA bus.