The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 1996

Filed:

Sep. 18, 1995
Applicant:
Inventors:

Claudio Diazzi, Milan, IT;

Fabrizio Martignoni, Varese, IT;

Mario Tarantola, Milan, IT;

Assignee:

SGS-Microelectronics S.r.l., Agrate Brianza, IT;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
327109 ; 327382 ; 327427 ; 327566 ;
Abstract

A circuit for controlling a power transistor connected in series with a load. The circuit comprises a control logic circuit which produces a signal at two levels with respect to a reference terminal, a level shifter connected between the control circuit and the power transistor, and which produces a signal at two levels referred to the node between the power transistor and the load. The level shifter includes a flip-flop the output of which controls the power transistor as well as two transistors driven by the control logic circuit to switch alternately and provide switching signals on the 'set' and 'reset' inputs of the flip-flop via two resistors. Two parasitic current generators inject current into the two resistors during the phase in which the power transistor is cut off. To prevent this current from causing unwanted switching of the flip-flop, a resistor connected to the 'set' terminal of the flip-flop has a lower resistance than that of the other resistor.


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