Latch-type current sense amplifier with self-regulating inputs

Abstract

A latch-type current sense amplifier circuit generates complementary latched data outputs indicative of a difference between first and second input currents provided to the sense amplifier circuit respectively via first and second input data lines. Included in the sense amplifier circuit are a latch circuit formed from cross-coupled inverters, a transmission gate responsive to a first control signal for equalizing the outputs of the sense amplifier circuit, and three transistors. The first transistor is responsive to a second control signal, activated after a delay after deactivation of the first control signal, for connecting a reference voltage to the latch circuit. The second transistor has a source connected to the first input data line, a drain connected to a first input of the latch circuit, and a gate connected to a second output of the latch circuit such that the second transistor is initially in a saturated conducting state immediately after deactivation of the first control signal and consequently, serves to reduce the effect of the high input impedance of the latch circuit. The third transistor has a source connected to the second input data line, a drain connected to a second input of the latch circuit, and a gate connected to a first output of the latch circuit such that the third transistor is also initially in a saturated conducting state immediately after deactivation of the first control signal and consequently, also serves to reduce the effect of the high input impedance of the latch circuit.