The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 1996

Filed:

Jun. 04, 1992
Applicant:
Inventors:

Mark J Foster, Lincoln Township, MI (US);

Saifuddin T Fakhruddin, St. Joseph, MI (US);

James L Walker, Benton Harbor, MI (US);

Matthew B Mendelow, St. Joseph, MI (US);

Jiming Sun, St. Joseph, MI (US);

Rodman S Brahman, St. Joseph Township, MI (US);

Michael P Krau, Hagar Township, MI (US);

Brian D Willoughby, Lincoln Township, MI (US);

Michael D Maddix, Lincoln Township, MI (US);

Steven L Belt, Stevensville, MI (US);

Scott A Hovey, St. Joseph, MI (US);

Mark A Ruthenbeck, Lincoln Township, MI (US);

Assignee:

Zenith Data Systems Corporation, Buffalo Grove, IL (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
395650 ; 395734 ; 395869 ; 3642399 ; 364240 ; 364246 ; 3642463 ; 3642624 ; 364231 ; 3642311 ; 3642314 ; 3642316 ; 3642421 ; 3642613 ; 364D / ; 364D / ;
Abstract

A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. The system includes a first interrupt mask register having a bit for indicating whether an interrupt is to be recognized by the processor, a second interrupt mask register having a bit for indicating whether the interrupt is to be recognized by a further circuit, and an arrangement responsive to a load of the first mask register for conforming the bit of the second mask register to the bit of the first mask register in a manner invisible to an application program being executed by the processor.


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