The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 1996

Filed:

Nov. 19, 1992
Applicant:
Inventors:

Hideyuki Iino, Kawasaki, JP;

Hiromasa Takahashi, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; G06F / ; G06F / ;
U.S. Cl.
CPC ...
395496 ; 395287 ; 395294 ; 395308 ; 395449 ; 395467 ; 395478 ; 395403 ; 395800 ; 3642318 ; 36424291 ; 36424292 ; 36424341 ; 36493541 ; 36493546 ; 36494834 ; 3649613 ; 36496426 ; 36496432 ; 364D / ; 364D / ; 36493151 ; 36423221 ;
Abstract

A memory accessing device is coupled to a first bus which connects a first buffer storage unit in a central processing unit to a second buffer storage unit. The memory accessing device can access, through the first bus, at least one of the first buffer storage unit and the second buffer storage unit independently of the central processing unit. The memory accessing device includes an address generating circuit for generating an address to access either or both of the first buffer storage unit and the second buffer storage unit. An output control unit in the memory accessing device outputs the address generated by the address generating circuit to the first bus. An output of the control unit enter an idle state if the second buffer storage unit issues a request for access to the first buffer storage unit when the memory accessing device obtains a right to use the first bus.


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