The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 1996
Filed:
Oct. 28, 1994
Applicant:
Inventor:
Nghia Tran, San Jose, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
371 214 ; 371 211 ; 36518522 ; 365201 ;
Abstract
The present invention provides a verification circuit for EEPROM cells by connecting PMOS verify transistors in parallel across the EEPROM cells to be tested. This configuration occupies less space on a PLD chip than prior verification circuits and allows all EEPROM bits associated with one logic cell in the PLD to be coupled to one verify path, minimizing logic complexity.
Tran, Nghia. (1996). Eeprom verification circuit with pmos transistors (U.S. Patent No. 5550842). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5550842
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile