The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 1996

Filed:

Jun. 03, 1994
Applicant:
Inventors:

Sujit Dey, Plainsboro, NJ (US);

Miodrag Potkonjak, Plainsboro, NJ (US);

Assignee:

NEC USA, Inc., Princeton, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364489 ; 364488 ;
Abstract

A method of high level circuit design synthesis using transformations based upon the addition of deflection operations reduces the interconnects and register requirements as well as the area requirements of a circuit design while preserving throughput without increasing the number of execution units needed. The method may also be applied to reduce the partial scan overhead for generating testable datapaths. The overall result of the transformations is to improve resource utilization and/or testability of circuits so designed.


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Dey, Sujit. (1996). High level circuit design synthesis using transformations (U.S. Patent No. 5550749). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5550749

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