The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 1996
Filed:
Mar. 01, 1995
Frank J Sweeney, Rowlett, TX (US);
Apparajan Ganesan, Manchacha, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A circuit and method to force an output of a logic circuit to a known state when its supply voltage rises above a predetermined level includes an MOS logic transistor (122) connected between the supply voltage (129) and the output line (130) and connected to receive an input signal (126) on its gate. An MOS state controlling transistor (124) of opposite conductivity type from the MOS logic transistor (122) is connected between the output line (130) and a reference potential (-V.sub.ss), with its gate connected to the gate of the MOS logic transistor (122). A resistor (132) is connected between the supply voltage (128) and the gate of the MOS state controlling transistor (124). If the supply voltage (128) rises above the predetermined level established by the threshold voltage of the MOS state controlling transistor, the MOS state controlling transistor (124) conducts to produce the reference potential on the output line (130). In one embodiment (120), the MOS state controlling transistor (124) is an NMOS transistor and the MOS logic transistor (122) is a PMOS transistor.