The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 1996
Filed:
Mar. 14, 1995
Applicant:
Inventor:
Norio Yoshida, Tokyo, JP;
Assignee:
NEC Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L / ;
U.S. Cl.
CPC ...
375372 ; 370102 ;
Abstract
A destuff circuit is provided with a virtual address counter wherein total number of destuff control pulses for each period T is supposed to be an average number Yn of actual occurrence averaged over latest nT durations. Read address signals are generated phase-locked with the output of the virtual write address counter.
Yoshida, Norio. (1996). Destuff circuit for asynchronous digital signals (U.S. Patent No. 5548624). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5548624
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile