High-speed carry increment adding device

Abstract

A high-speed carry increment adding device having a first module including a first adder, the first adder adding a desired number of first bit inputs and generating a plurality of partitioned sums and a partitioned carry as a result of the addition, and a second module including a second adder and a conditional incrementer, the second adder adding a desired number of second bit inputs regardless of the partitioned carry from the first adder and generating a plurality of partitioned sums and a partitioned carry as a result of the addition, the conditional incrementer inputting the partitioned carry from the first adder as an increment signal and incrementing the partitioned sums from the second adder in response to the inputted increment signal. Also, the second module includes a partitioned sum detector for detecting whether all of the partitioned sums from the second adder are '1' and generating a partitioned sum detect signal in accordance with the detected result. Also, the adding device includes at least one module arranged at a stage subsequent to and in parallel to the second module, the at least one module having the same construction as that of the second module, and an increment signal generator for generating the increment signal to the conditional incrementer of a desired one of the modules.