Multistream instruction processor able to reduce interlocks by having a

Abstract

The present invention discloses a multistream instruction processor issuing instructions from N instruction streams in parallel, and processing instruction streams interchangeably when the number of the instruction streams is N or larger than N. Such processor comprises aninstructionpreparationunit comprised of N thread slots each of which fetches/decodes instructions from the instruction stream assigned thereto as well as issues decoding result one at a time; a functional unit comprised of M instruction execution units each of which executes instructions in accordance with the decoding result of the thread slot; an execution connection unit for replacing a connection with another, the connection between the instruction preparation unit and the functional unit so that the result received from the thread slot will be provided to the execution unit which is ready to execute it; and an instruction stream controller comprised of a context backup memory and an exchange controller, the context backup memory holding a context of the instruction stream which indicates how far execution of the instruction stream had been conducted so that the instruction stream will be re-executed while the exchange controller extracting the context of the instruction stream and temporarily storing it into the context backup memory when a predetermined event happens in the instruction therefrom as well as making the instruction execution unit receive another instruction, the instruction execution unit which was executing the instruction including the predetermined event.