Cell architecture for built-in self-test of application specific

Abstract

An application specific integrated circuit (ASIC) includes ASIC logic, test logic, dual function input test cells and dual function output test cells. The test logic with the input and output test cells provides manufacturing test capability for the ASIC logic with a plurality of input pins and a plurality of output pins while reducing both the gate count and signal time delay associated with the input and output test cells. Each input test cell includes a boundary scan circuit means and a built-in self-test circuit means. An input test cell has a signal propagation time delay for a signal, that travels from an input pin to an ASIC logic input line, equivalent to one two-to-one multiplexer signal propagation delay. Hence, while the input test cell has the capability of both built-in self-test and boundary scan testing, the dual capability is achieved without incurring a signal propagation time delay for each capability. Like the input test cells, each output test cell includes a boundary scan circuit means and a built-in self-test circuit means. The output test cell also has a signal propagation time delay for a signal, that travels from an ASIC logic output line to an output pin, equivalent to a single two-to-one multiplexer signal propagation delay.